Reconfigurable Computing

This page was born out of an ECE311 report on the subject of Reconfigurable Computing. And here is the outline.

Here is a handy page of Reconfigurable Computing references.

ACE

SigArch attempted our own naive entrance into Reconfigurable computing in Spring of 1994, entitled ACE, the Apropos Computational Engine. ACE was a 5x5 array of Xilinx XC3020 and XC3030 FPGAs (which we got for free) with associated RAM, interfaced to a host PC over PCI. We halted development once we realized that the interconnect speed overhead would be daunting.

ACE II

ACE II is a future project idea, that may be feasible once the Xilinx 6200-series parts become available. We want to use a few of the parts (with the way-bitchin FASTmap DPGA technology) and directly map them into the address-space of a computer (perhaps through a DRAM emulator) for way-bitchin superbad fast reconfigurable computing.

sigarch@uiuc.edu